TSC warp, Threads

[Achim Gratz]

Hal Murray via devel writes:
> Can you say more.  Is there any good Intel documentation that says "Xeon v3 
> and up"?

Not that I know of, although it's surely buried inside some file
someplace on ARK.

> Or anything that describes which families or chips will/won't do what
> I want?

The trouble with that type of question is that a significant part of the
stuff that might throw off the TSC from how you want it to be have
resides in different parts of the hardware (core, uncore, chipset) and
gets controlled by software.

> My search process would be a lot simpler if I could just say "Haswell or 
> newer".

Let's say these have been solid for me and I haven't heard a lot of
noises the other way.  At least the big names should have their BIOS
updated to have all the latest fixes.

> I have Ivy Bridge and Sandy Bridge PCs without warp.
>     i7-3770, i5-3570, and i3-2120
> Those are Core rather than Xeon.

I haven't laid my hands on a Sandy Xeon but I think the desktop variants
for Sandy have larger differences to the server counterparts than for
Haswell.

> There is an Intel erratum doc that sounds like it is fixing the problem I'm 
> having.

Doesn't sound likely to me.  The kernel messages you've shown seem to
indicate that different processors (in the same package apparently) have
different TSC values.  That sort of thing is sometimes caused by SMM
code (from BIOS) that tries to hide the cycles it is spending.  There is
another message that seems to indicate that an attempt to correct for
that offset failed, so either no tsc_adjust feature or more interference
from code that runs outside the kernel.


Regards,
Achim.
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