TSC warp, Threads

[Hal Murray]

Thanks.

> That's an IvyBridge I think, you will want Haswell or later.
> Haswell and later are OK (Xeon v3 and up) AFAIK

Can you say more.  Is there any good Intel documentation that says "Xeon v3 
and up"?
Or anything that describes which families or chips will/won't do what I want?

My search process would be a lot simpler if I could just say "Haswell or 
newer".

I have Ivy Bridge and Sandy Bridge PCs without warp.
    i7-3770, i5-3570, and i3-2120
Those are Core rather than Xeon.


There is an Intel erratum doc that sounds like it is fixing the problem I'm 
having.

Intel® Xeon® Processor E5 Product Family
Specification Update
May 2020
Revision 021
https://www.intel.com/content/dam/www/public/us/en/documents/specification-upda
tes/xeon-e5-family-spec-update.pdf

BT81.  TSC is Not Affected by Warm Reset
Problem:  The  TSC  (Time  Stamp  Counter  MSR  10H)  should be cleared on 
reset. Due to this erratum the TSC is not affected by warm reset.
Implication:  The  TSC  is  not  cleared  by  a  warm  reset.  The  TSC  is  
cleared  by  power-on  reset  as expected. Intel has not observed any 
functional failures due to this erratum.
Workaround:  None identified.
Status:  For the affected steppings, see the Summary Tables of Changes

The similar doc for v2 calls it CA105
Intel® Xeon® Processor E5 v2 Product Family
https://www.intel.com/content/dam/www/public/us/en/documents/specification-upda
tes/xeon-e5-v2-spec-update.pdf



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