[ntp:hackers] u-blox reference clock driver

Gary E. Miller gem at rellim.com
Mon Aug 13 00:49:53 UTC 2018

Yo Achim!

On Sun, 12 Aug 2018 09:33:36 +0200
Achim Gratz via devel <devel at ntpsec.org> wrote:

> > The results are an average PPS jitter of 222 ns!  
> Well, yes -- if you measure and eliminate the interrupt latency, which
> by far dominates the jitter in the normal PPS processing, then the
> residual jitter goes down.

I'll take it!  One good step at a time.

> The missed opportunity with this implementation is that you could
> actually measure both the raw system clock frequency and the (NTP
> corrected) phase independently and thus improve the convergence of the
> FLL/PLL algorithm significantly by using both the rising and falling
> edge measurement.

The ntpd convergence has always bugged me a lot.  But since most time
nuts never power down their gear they ignore this part of the problem.

> It's also unfortunate that apparently no attempt was made to

Suggest that for his PhD thesis.

I'll be happy if we can get a copy of his code.

Gary E. Miller Rellim 109 NW Wilmington Ave., Suite E, Bend, OR 97703
	gem at rellim.com  Tel:+1 541 382 8588

	    Veritas liberabit vos. -- Quid est veritas?
    "If you can’t measure it, you can’t improve it." - Lord Kelvin
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