NTPsec leap second experience

[Eric S. Raymond]

Hal Murray <hmurray at megapathdsl.net>:
> 
> > I'm somewhat embarrassed to admit that I have understood very little of your
> > exposition about this.  I'm a software systems architect, not a metrologist,
> > and the stuff going on down at the PLL level is still a bit beyond my ken.
> 
> The field is complex.  There are big thick textbooks on it.
> 
> Wikipedia has a couple of good articles.
> 
> Phase-locked loop
>   https://en.wikipedia.org/wiki/Phase-locked_loop
> 
> PID controller
>   https://en.wikipedia.org/wiki/PID_controller

Thanks, I'll read those.  Actually, re-read the first and read the second.

> The usual problem with badly designed/implemented PLLs is that they
> oscillate.  A less evil problem is overshoot.  You may be willing to
> trade some overshoot to gain faster response.
>
>  The bump option in ntpfrob lets you see what the PLL does in
> response to an error signal.

Please consider writing a PLL entry for the glossary that includes
these pointers and also distills some of your field experience.

> esr at thyrsus.com said:
> > However, what I *do* take away is that our drastic reduction surgery on the
> > rest of the suite apparently has not accidentally damaged the PLL nor
> > screwed up its convergence properties. I find that very reassuring. 
> 
> I'm pretty sure that somebody would have noticed if we had really
> broken something in that area.

One would think so, yes.  But in this area the stakes are sufficiently
high and I am sufficiently doubtful of my own ability to generate useful
insights that I frankly welcome all the reassurance I can get.
-- 
		<a href="http://www.catb.org/~esr/">Eric S. Raymond</a>