New tour-document section explaining the clock interface and PLL.
Eric S. Raymond
esr at thyrsus.com
Wed Sep 28 21:30:45 UTC 2016
Gary E. Miller <gem at rellim.com>:
> Yo Eric!
> On Wed, 28 Sep 2016 16:32:33 -0400
> "Eric S. Raymond" <esr at thyrsus.com> wrote:
> > The slewing variations in clock speed are
> > so small that they're generally invisible even to soft-realtime
> > applications.
> Got a number on this? chronyd can slew the clock up to 8.5% for
> extended periods of time.
I do not have a number. You can supply one, I think.
> > The KERNEL_PLL code can produce
> > much faster convergence from a cold start.
> For currently unknwon reasons.
And that's our hope for an eventual way out of this mess.
As for the rest, you and Hal should argue it out and patch that exposition
until it's better. Please don't expect me to do all the editing; I have
other tasks piled up higher than my eyebrows.
<a href="http://www.catb.org/~esr/">Eric S. Raymond</a>
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